1. Field of the Invention
The present invention relates to a method of manufacturing a flash memory. More particularly, the present invention relates to a method of manufacturing a flash memory with a shallow trench isolation and a buried bit line.
2. Description of the Related Art
Electrically erasable programmable read-only-memories (EEPROMs) are widely used as memory components for personal computers and electronic equipment. A conventional EEPROM memory cell comprises a floating gate transistor structure that is programmable, erasable and able to store data. The EEPROM device allows data or programs to be erased or written in a bit by bit manner. However, the conventional EEPROM suffers from a slow storage and retrieval time of typically around 150 ns to 200 ns. Recently, a faster EEPROM, such as a flash memory, has been developed having a storage and retrieval time of about 70 ns to 80 ns. By using the flash memory, the data or programs are erased or written in a block by block manner. Only one or two seconds are needed to compete an erasing action. This can save much time and has a lower fabrication cost.
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. Conventionally, the local oxidation of silicon (LOCOS) technique is widely utilized in the semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for quite a period of time, it is one of the most reliable and low-cost methods for fabricating device isolation region. However, there are still some drawbacks to LOCOS. The drawbacks include internal stress generation and bird's beak encroachment. For a highly integrated device, the problem of bird's beak encroachment by isolation regions is especially difficult to avoid; thus the isolation regions cannot effectively isolate devices. Additionally, the conventional method for forming a buried bit line is to form a doped region for a bit line by an implantation step before the isolation region is formed. However, when the subsequent thermal process, such as formation of the oxide layer and liner oxide layer and the densification step, is performed, the lateral diffusion of the doped region will occur. Therefore, the short channel effect happens.